1. Field of the Invention
The present invention relates generally to driver circuits for providing predetermined output voltages corresponding to respective output load impedances depending on fluctuations in output load.
2. Description of the Background Art
FIG. 1 is a diagram showing a structure of a basic interface of an ISDN (Integrated Services Digital Network) described in Recommendation I. 430 of the CCITT. This basic interface of the ISDN is employed for high-speed digital communication using the existing two-wire telephone line (subscriber's line) at a data rate of 192 Kbps.
In FIG. 1, a station 300 and a network termination 200 are connected through a subscriber's line 500. A maximum of 8 terminal equipments 100 are connected to the network termination 200 through a subscriber's bus 400. The network termination 200 and each of the terminal equipments 100 are respectively provided with driver circuits line drivers) 10 for respectively driving the subscriber's bus 400. Outputs of the driver circuits 10 in the eight terminal equipments 100 are connected in parallel to an input of the network termination 200. An output of the driver circuit 10 in the network termination 200 is connected to inputs of the eight terminal equipments 100. Thus, an output load impedance of each of the driver circuits 10 is changed depending on an operating state of another terminal equipment 100 or the network termination 200.
According to the Recommendation I. 430 of the CCITT, a pulse mask showing an allowable value of an output pulse shape of a driver circuit is determined for cases where load impedances are respectively 5.6.OMEGA., 50.OMEGA. and 400.OMEGA.. FIG. 2A shows the pulse mask at the time of the load of 50.OMEGA., and FIG. 2B shows the pulse mask at the time of the load of 400.OMEGA.. FIGS. 2A and 2B mean that the output pulse shape must be included in an allowable region encircled by hatching. In addition, it is determined that an amplitude value (peak value) of the output pulse at the time of the load of 5.6.OMEGA. must be 20% (150mV) or less of an amplitude value of a nominal pulse shown in FIG. 2A. As obvious from FIGS. 2A and 2B, the amplitude value of the output pulse must be 150mV or less at the time of the load of 5.6.OMEGA., in the range of 675 to 825mV at the time of the load of 50.OMEGA., and in the range of 675 to 1200mV at the time of the load of 400.OMEGA.. Thus, an output voltage of the driver circuit 10 must be changed depending on the load impedance.
FIG. 3 is a diagram showing one example of a driver circuit satisfying the above described determination, which is described in, for example, Proceedings of 1986 National Conference of Institute of Electronics and Communication Engineers of Japan (2013, pp. 9-42).
In FIG. 3, when an input signal I.sub.+ attains an "H" level, a potential difference .DELTA.V occurs between a base of a bipolar transistor Q7 and a base of a bipolar transistor Q8. Since the bipolar transistor has the property that a voltage between base and emitter becomes constant, i.e., approximately 0.6V at the on-time, this potential difference .DELTA.V is applied between primary terminals of a pulse transformer PT1 without any fluctuations. Consequently, a voltage of a value obtained by dividing the potential difference .DELTA.V by the turns ratio appears between secondary output terminals O1 and O2. Therefore, if a load impedance of a load connected between the output terminals O1 and O2 varies, an equal voltage is outputted. Thus, if the circuit constant is set such that a voltage appearing between the output terminals O1 and O2 becomes 750mV, a pulse mask at the time of the loads of 50.OMEGA. and 400.OMEGA. can be satisfied.
On the other hand, when the load impedance becomes small, current flowing through the pulse transformer PT1 attempts to increase to keep the voltage between the output terminals O1 and O2 at a constant voltage. However, base potentials are respectively applied to bipolar transistors Q9 and Q10 by diodes D1 and D2. Therefore, current of a given value or more does not flow through the transistors Q9 and Q10. Thus, the current flowing through the transistors Q9 and Q10 is limited, so that a voltage of the output pulse at the time of the load of 5.6.OMEGA. is suppressed to 150mV or less. Meanwhile, at the time of the loads of 50.OMEGA. and 400.OMEGA., the current flowing through the transistors Q9 and Q10 is less, so that the above described current limiting mechanism does not work.
Additionally, when an input signal I.sub.- is brought to the "H" level, pulses in the opposite directions are respectively outputted from the output terminals O1 and O2. Thus, in this driver circuit, a pulse of both positive and negative polarities can be outputted.
However, the above described driver circuit is constituted by a bipolar transistor. Thus, in order to form this driver circuit, along with another digital circuit, as an LSI (Large-Scaled Integrated Circuit), the digital circuit must be constituted by a bipolar device, or a digital circuit comprising a MOS device and a driver circuit comprising a bipolar device must be incorporated with each other in hybrid configuration using a special process such as an expensive Bi-CMOS (Bipolar-Complementary Metal Oxide Semiconductor) process. With respect to a large-scaled digital circuit, it is desirable that the digital circuit is constituted by a CMOS device, in which case the cost is lowered, and high density and low power consumption can be achieved. Thus, in either one of the above described methods, the cost is raised in order to form a driver circuit, along with another digital circuit, as an LSI.
Additionally, FIG. 4 is a diagram showing another example of the driver circuit satisfying the pulse mask in Recommendation I. 430 of the CCITT. This driver circuit is described in DIGEST OF TECHNICAL PAPERS OF 1988 IEEE International Solid-State Circuits Conference, pp. 108-109, pp. 317. This driver circuit comprises two controllable current sources J1 and J2, MOS transistors Q11 and Q12 constituting a first current mirror circuit, and MOS transistors Q13 and Q14 constituting a second current mirror circuit. A pulse is outputted between output terminals O1 and O2 connected to a secondary side of a pulse transformer Tx in response to a control signal applied to the current source J1 or a control signal applied to the current source J2.
In this driver circuit, a pulse voltage is adjusted by current control. Current flowing through the pulse transformer Tx is determined depending on resistance values of resisters R6 to R8 and the MOS transistors Q11 to Q14. However, it seems that it is difficult to precisely set the resistance values of the devices to predetermine values, respectively, in manufacturing processes. In addition, the resistance values of the devices are changed depending on the temperature. Thus, adjustment is required. In general, it is more difficult in circuit techniques to precisely keep constant current flowing through a circuit, as compared with to precisely keep constant a voltage.